1. Field of the Invention
The present invention relates to an integrated circuit (IC) carrier for testing an IC, more specifically to IC carriers for a flat package (QFP, SOP) and a pin grid array package (PGA) having a closely arranged fine lead array.
2. Description of the Prior Art
Since it is easy for closely arranged fine leads in an array projected out of an IC package to be bent by handling, electric testing is usually carried out by loading an IC package on an IC carrier. FIG. 1A shows a conventional IC carrier 1 for a QFP type package 2 having a flat lead array 3, and the IC carrier has an array of sockets 4. FIG. 1B shows an enlarged part of the array of sockets where a lead 30 is inserted in a socket 50 between separation walls 40. FIG. 1C shows a cross-sectional view of the socket array by looking at it in the direction of arrows X.sub.1 and Y.sub.1 indicated in FIG. 1A. All sockets in an array have the same inner width denoted by A.sub.1 between separation walls 40. FIG. 2A shows also a conventional IC carrier 7 for a PGA type package 8 having a two dimensional array of leads 9, and the IC carrier has a two dimensional array of sockets 10. FIG. 2B shows an enlarged part of the array of sockets where a lead 90 is inserted into a socket 100. FIG. 2C shows a cross-sectional view of the socket array by looking at it in the direction of arrows X.sub.2 and Y.sub.2 indicated in FIG. 2A. All sockets 100 in an array have the same inner diameter denoted by B.sub.1 with a tapered side-wall 11.
Since each of leads of an IC package in either type is arranged closely and tightly inserted into a socket, the outward stress on the side wall of each socket accumulates successively and resultantly makes the position of sockets in outer portion of an array displace outward considerably. Alternately, when the closely arranged fine leads are inserted in the socket, it often happens at an initial stage of the insertion that leads in some part of an array are already inserted, while leads in some other part of the same array are not inserted yet. Consequently, the uninserted lead may push laterally the separation (or side) wall excessively enough to be deformed. Particularly, if an allowable error in a lead array has an opposite direction to that in the relevant socket array, smooth loading or unloading of IC package becomes harder without deformation of leads.